High-Speed Link Design, Then and Now

For the past 13 years, my research has included the design of high-speed chip-to-chip communication links. When this work started, most chip I/O were TTL levels, and ran at tens of MHz. Our initial work focused on understanding the basic problems of chip I/O, creating the needed circuit blocks to solve these problems, and predicting how the performance would scale with technology. Today the situation is quite different. The basic issues are well understood, and there are many variants of the needed circuit blocks. However the speed demands have also grown with time, causing new issues to arise, and forcing the resulting designs to grow dramatically in complexity. This talk will review the basic issues of a high-speed link, first looking at the problems of link design 10 years ago. After describing how the basic issues of timing and signaling are addressed and how these solution scale, I will look at the issues that designers are facing today, and the techniques being used to cope with these problems. These issues include: circuits limited by the bandwidth of the external wires, worsening transistor matching, and rising bandwidth requirements. The talk will close with some projections about the future, and will look at both electronic and optical links.